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Features
* 3 identical bidirectional link channels allowing full duplex communication under
selectable transmit rate from 1.25 up to 200 Mbit/s in each direction
* A COmmunication Memory Interface (COMI) provides autonomous accesses to a * * * * * * * *
communication memory which are controlled by an arbitration unit, allowing two TSS901E to share one Dual Port Ram without external arbitration The scalable databus width (8/16/32 bit) allows flexible integration with any CPU type Little or big endian mode is configurable AHOst Control Interface (HOCI) gives read/write accesses to the TSS901E configuration registers and to the DS-link channels for the controlling CPU Device control via one of the three links allows its use in systems without a local controller Link disconnect detection and parity check at token (data and control) level; possible checksum generation for packet level check Power saving mode relying on automatic transmit rate reduction Auser's manual of the TSS901E (also called SMCS332) is available at: http://www.omimo.be/companies/dasa_000.htm Designed on Atmel MG1140E matrix and packaged into MQFPL196
Tripple Point to Point IEEE 1355 High Speed Controller
Description and Applications
The TSS901E provides an interface between a Data-Strobe link - according to the IEEE Std 1355-1995 specification carrying a simple interprocessor communication protocol - and a data processing node consisting of a CPU and a communication and data memory. The TSS901E offers hardware supported execution of the major parts of the interprocessor communication protocol: data transfer between two nodes of a multi-processor system is performed with minimal host CPU intervention. The TSS901E can execute simple commands to provide basic features for system control functions; a provision of fault tolerant features exists as well. Although the TSS901E initial exploitation is for use in multi-processor systems where the high speed links standardisation is an important issue and where reliability is a requirement, it could be used in applications such as heterogeneous systems or modules without any communication feature like special image compression chips, some signal processors, application specific programmable logic or mass memory. The TSS901E may also be used in single board systems where standardised high speed interfaces are needed and systems containing "non-intelligent" modules such as A/D-converter or sensor interfaces which can be assembled with the TSS901E thanks to the "control by link" feature.
TSS901E
Rev. C - 24-Aug-01
1
TSS901E
Introduction
The TSS901E provides an interface between a Data-Strobe link according to the IEEE Std 1355-1995 specification carrying the simple interprocessor communication protocol (1) and a data processing node consisting of a CPU and communication and data memory. The TSS901E provides HW supported execution of the major parts of the simple interprocessor communication protocol, particularly: * * * transfer of data between two modes of a multi-processor system with minimal host CPU intervention, execution of simple commands to provide basic features for system control functions, provision of fault tolerant features.
However, with disabling of features such as the protocol handling or with reduction of the transmit rate (TSS901E automatically reduces transmit rate for sending null tokens) also low power usage is supported. Figure 1. TSS901E Block Diagram
Receive COMI RX1_DS TX1_DS DS macro cell
CADR CCTRL CDATA
Protocol
HADR HCTRL Transmit HOCI Channel 1 HINT HDATA
RX2_DS TX2_DS Channel 2 PRCI
RCPU SES
UTIL RX3_DS TX3_DS Channel 3 Test
JTAG
Target applications are heterogeneous multi-processor systems supported by scalable interfaces including the little/big endian swapping. The TSS901E connects modules with different processors (e.g. TSC21020F, ERC32, TSC695E and others). Any kind of network topology could be realized through the high speed point-to-point IEEE1355-links (see chapter Applications).
1. Rastetter P. et.al., Simple Interprocessor Communication Protocol Specification, DIPSAPII-DAS-31-01, Issue 3, 08.10.96, also available on the same web site as the users guide.
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Rev. C - 24-Aug-01
Interfaces
The TSS901E consists of the following blocks (See Figure 1): * bidirectional link channels, all comprising the DS-link macro cell (DSM), receive and transmit sections (each including FIFOs) and a protocol processing unit (PPU). Each channel allows full duplex communication up to 200 Mbit/s in each direction. With protocol command execution a higher level of communication is supported. Link disconnect detection and parity check at token level are performed. A checksum generation for a check at packet level can be enabled. The transmit rate is selectable between 1.25 and 200 Mbit/s; an additional power saving mode can be enabled, where the transmit rate is automatically reduced to 10 Mbit/s when only Null tokens are being transmitted over the link. The default transmit rate is 10 Mbit/s. For special applications the data transmit rate can be programmed to values even below 10 Mbit/s; the lowest possible (to be within the IEEE-1355 specification) transmit rate is 1.25 Mbit/s (the next values are 2.5 and 5 Mbit/s). * Communication Memory Interface (COMI) performs autonomous accesses to the communication memory of the module to store data received via the links or to read data to be transmitted via the links. The COMI consists of individual memory address generators for the receive and transmit direction of every DS link channel. The access to the memory is controlled via an arbitration unit providing a fair arbitration scheme. Two TSS901E can share one DPRAM without external arbitration. The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type. Operation in little or big endian mode is configurable through internal registers. The COMI address bus is 16 bit wide allowing direct access of up to 64K words of the DPRAM. Two chip select signals are provided to allow splitting of the 64k address space in two memory banks. * Host Control Interface (HOCI) gives read and write access to the TSS901E configuration registers and to the DS-link channels for the controlling CPU. Viewed from the CPU, the interface behaves like a peripheral that generates acknowledges to synchronize the data transfers and which is located somewhere in the CPU's address space. Packets can be transmitted or received directly via the HOCI. In this case the Communication Memory (DPRAM) is not strictly needed. However, in this case the packet size should be limited to avoid frequent CPU interaction. The data bus width is scalable (8/16/32 bit) to allow flexible integration with any CPU type. The byte alignment can be configured for little or big endian mode through an external pin. Additionally the HOCI contains the interrupt signalling capability of the TSS901E by providing an interrupt output, the interrupt status register and interrupt mask register to the local CPU. A special pin is provided to select between control of the TSS901E by HOCI or by link. If control by link is enabled, the host data bus functions as a 32-bit general purpose interface (GPIO). * * Protocol Command Interface (PRCI) that collects the decoded commands from all PPUs and forwards them to external circuitry via 5 special pins. JTAG Test Interface that represents the boundary scan testing provisions specified by IEEE Standard 1149.1 of the Joint Testing Action Group (JTAG). The TSS901E' test access port and on-chip circuitry is fully compliant with the IEEE 1149.1 specification. The test access port enables boundary scan testing of circuitry connected to the TSS901E I/O pins.
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TSS901E
Rev. C - 24-Aug-01
TSS901E
Operation Modes
According to the different protocol formats expected for the operation of the TSS901E, two major operation modes are implemented into the TSS901E. The operation modes are chosen individually for each link channel by setting the respective configuration registers via the HOCI or via the link. * Transparent Mode (default after reset): This mode allows complete transparent data transfer between two nodes without performing any interpretation of the databytes and without generating any acknowledges. It is completely up to the host CPU to interpret the received data and to generate acknowledges if required. The TSS901E accepts EOP1 and EOP2 control tokens as packet delimiters and generates autonomously EOP1/EOP2 (as configured) markers after each end of a transmission packet. This mode also includes as a special submode: - * Wormhole routing: This mode allows hardware routing of packets by the TSS901E.
Simple Interprocessor Communication (SIC) Protocol Mode: This mode executes the simple interprocessor communication protocol as described in the protocol specification (1). The following capabilities of the protocol are implemented into the TSS901E: - - - interpretation of the first 4 data tokens as the header bytes of the protocol autonomous execution of the simple control commands as described in the protocol specification(1) autonomous acknowledgement of received packets if configured
In transmit direction no interpretation of the data is performed. This means that for transmit packets, the four header bytes must be generated by the host CPU and must be available as the first data read from the communication memory. EOP1/EOP2 control tokens are automatically inserted by the TSS901E when one configured transfer from the communication memory has finished.
1.
Rastetter P. et.al., Simple Interprocessor Communication Protocol Specification, DIPSAPII-DAS-31-01, Issue 3, 08.10.96, also available on the same web site as the users guide.
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Rev. C - 24-Aug-01
TSS901E Control by Link A feature of the TSS901E is the possibility to control the TSS901E not only via HOCI but
via one of the three links. This allows to use the TSS901E in systems without a local controller (Controller, FPGA etc.). Since the HOCI is no longer used in this operation mode, it is instead available as a set of general purpose I/O (GPIO) lines.
Wormhole Routing
The TSS901E introduces a wormhole routing function similar to the routing implemented in the ST-Microelectronics C104 routing switch. Each of the three links and the TSS901E itself can be assigned an eight bit address. When routing is enabled in the TSS901E, the first byte of a packet will be interpreted as the address destination byte, analysed and removed from the packet (header deletion). If this address matches one of the two other link addresses or the TSS901E address assigned previously, the packet will be automatically forwarded to this link or the FIFO of the TSS901E. If the header byte does not match a link address, the packet will be written to the internal FIFO as well and an error interrupt (maskable) will be raised. Since the Protocol Processing Unit (PPU) determines a major part of the TSS901E functionality, the principal blocks of the PPU and their function are described here. This functionality is provided for every DS link channel of the TSS901E. * Protocol Execution Unit: This unit serves as the main controller of the PPU block. It receives the tokens from the DS macrocell and interprets (in protocol mode) the four header data characters received after an EOP1/EOP2 control character. If the address field matches the link channel address and the command field contains a valid command then forwarding of data into the receive FIFO is enabled. If the command field contains a "simple control command" then the execution request is forwarded to the command execution unit. The protocol execution unit also enables forwarding of header data characters to the acknowledge generator and provides an error signal in case of address mismatch, wrong commands or disabled safety critical "simple control commands". The protocol execution unit is disabled in "transparent" or "wormhole routing" operation mode. * Receive, Transmit, Acknowledge: The transmit and receive FIFOs decouple the DS link related operations from the TSS901E related operations in all modes and such allows to keep the speed of the different units even when the source or sink of data is temporarily blocked. In the protocol mode a further FIFO (acknowledge FIFO) is used to decouple sending of acknowledges from receiving new data when the transmit path is currently occupied by a running packet transmission. * Command Execution Unit: This unit performs activating resp. deactivating of the CPU reset and the specific external signals and provides the capability to reset one or all links inside the TSS901E, all actions requested by the decoded commands from the protocol execution unit. The unit contains a register controlling the enable/disable state of safety critical commands which is set into the 'enable' state upon command request and which is reset after a safety critical command has been executed. The CPU reset and the specific external signals are forwarded to the Protocol Command Interface (PRCI).
PPU Functional Description
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TSS901E
Rev. C - 24-Aug-01
TSS901E
Fault Tolerance
The IEEE Std 1355-1995 specifies low level checks as link disconnect detection and parity check at token level. The TSS901E provides, through the Protocol Processing Unit, features to reset a link or all links inside the TSS901E, to reset the local CPU or to send special signals to the CPU commanded via the links. Additionally it is possible to enable a checksum coder/decoder to have fault detection capabilities at packet level.
Applications
The TSS901E is a very high speed, scalable link-interface chip with fault tolerance features. The initial exploitation is for use in multi-processor systems where the standardisation or the high speed of the links is an important issue and where reliability is a requirement. Further application examples are heterogeneous systems or modules without any communication features as special image compression chips, certain signal processors (TSC21020F, ERC32, ...), application specific programmable logic or mass memory. The TSS901E could also be used for single board systems where standardised high speed interfaces are needed. Even "non-intelligent" modules such as A/D-converter or sensor interfaces can be assembled with the TSS901E because of the "control by link" feature. The complete control of the TSS901E can be done via link from a central controller-node.
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Rev. C - 24-Aug-01
Register Set
This chapter describes the TSS901E registers which can be read or written by the HOCI or via the link (in case the "control by link" is enabled) to control TSS901E operations. All TSS901E control operations are performed by writes or reads of the respective registers. Most of the control operations are obvious from the content of the registers. General Conventions: * * * bit 0 (D0) = least significant bit, bit 7 (D7) = most significant bit (or bit 15 resp. bit 31) D x:0 means data bit x until bit 0.
Access by HOCI: HOCI data transfer
Big/Little endian selection of the HOCI is done using a special pin (HOSTBIGE) of the TSS901E. By connecting this pin to either Vcc or GND the HOCI is configured to be in little or big endian mode as follows: When Signal HOSTBIGE = '0' (GND), the HOCI data port is in little endian mode. When Signal HOSTBIGE = '1' (Vcc), the HOCI data port is in big endian mode. Little endian mode selected: * * 8 bit data port (default after reset) - - - * - - - - * * register byte 0 is connected with pin HDATA0 - HDATA7 register byte 0 is connected with pin HDATA0 - HDATA7 register byte 1 is connected with pin HDATA8 - HDATA15 register byte 0 is connected with pin HDATA0 - HDATA7 register byte 1 is connected with pin HDATA8 - HDATA15 register byte 2 is connected with pin HDATA16 - HDATA23 register byte 3 is connected with pin HDATA24 - HDATA31 16 bit data port
32 bit data port
Big endian mode selected: 8 bit data port (default after reset) - - - * - - - - register byte 0 is connected with pin HDATA24 - HDATA31 register byte 0 is connected with pin HDATA24 - HDATA31 register byte 1 is connected with pin HDATA16 - HDATA23 register byte 0 is connected with pin HDATA24 - HDATA31 register byte 1 is connected with pin HDATA16 - HDATA23 register byte 2 is connected with pin HDATA8 - HDATA15 register byte 3 is connected with pin HDATA0 - HDATA7 16 bit data port
32 bit data port
The registers of the TSS901E are 1, 2 or 4 Bytes wide. That means, if the HOCI data port is in 8 bit mode, 4 read or write accesses are necessary to access a 4 Byte register (e. g. the interrupt mask register). In 16/32 bit mode the data bits 31 - 8 are '0' if an 8 bit register is read.
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TSS901E
Rev. C - 24-Aug-01
TSS901E
Register Address Map
The addresses of the TSS901E registers are directly mapped with pins HADR7 - 0. The tables below shows the addresses of all the TSS901E registers depending on the HOCI port width. TSS901E status and control registers
Port Width / Address (hex) 32 00 01 02 03 16 00 01 02 03 04 04 06 8 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F COMI_ACR PRCIR COMI_CS0R COMI Chip Select 0 upper address boundary Register reserved COMI Arbitration Control Register PRCI Register FF 00 08 00 r/w r/w r/w IMR Interrupt Mask Register 00000000 r/w ISR Interrupt Status Register 04010040 ro Register SICR TRS_CTRL ROUTE_CTRL Function TSS901E Interface Control Register Transmit-Speed-Base Register Routing Enable / Status Register reserved Reset Value (hex) 00 0A 00 00 Access r/w r/w r
08 08 0A
0C 0D 0E 0F
0C 0D 0E 0F
TSS901E channel 1 status and control registers
Port Width / Address (hex) 32 10 11 12 13 14 15 16 17 16 10 11 12 13 14 15 16 17 8 10 11 12 13 14 15 16 17 Register CH1_DSM_MODR CH1_DSM_CMDR CH1_DSM_STAR CH1_DSM_TSTR CH1_ADDR CH1_RT_ADDR CH1_PR_STAR Function channel 1 DSM mode Register channel 1 DSM command Register channel 1 DSM status Register channel 1 DSM test Register channel 1 address Register channel 1 Route Address Register channel 1 Protocol Status Register reserved Reset Value (hex) 03 00 00 00 00 00 04 00 Access r/w r/w r/w r/w r/w r/w r/w ---
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Rev. C - 24-Aug-01
Port Width / Address (hex) 32 18 19 1A 1B 1C 1D 1E 1F 20 16 18 19 1A 1B 1C 1D 1E 1F 20 8 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F CH1_COMICFG CH1_TX_SAR Register CH1_CNTRL1 CH1_CNTRL2 CH1_HTID CH1_HCNTRL CH1_ESR1 CH1_ESR2 Function channel 1 control Register 1 channel 1 control Register 2 channel 1 Header Transaction ID byte channel 1 Header control byte channel 1 detailed error source register 1 channel 1 detailed error source register 2 reserved channel 1 COMI configuration register channel 1 transmit Start Address Register Reset Value (hex) 00 00 00 00 00 00 00 00 0000 Access r/w r/w ro ro r/w r/w --r/w r/w
22
22
CH1_TX_EAR
channel 1 transmit End Address Register
0000
r/w
24 26 27 28
24 26 27 28
CH1_TX_CAR CH1_TX_FIFO CH1_TX_EOPB CH1_RX_SAR
channel 1 transmit Current Address Register channel 1 transmit FIFO channel 1 transmit EOP Bit Register channel 1 receive Start Address Register
0000 --0000
ro wo wo r/w
2A
2A
CH1_RX_EAR
channel 1 receive End Address Register
0000
r/w
2C 2E 2F
2C 2E 2F
CH1_RX_CAR CH1_RX_FIFO CH1_STAR
channel 1 receive Current Address Register channel 1 receive FIFO channel 1 Status Register
0000 xxxxxxxx 01
ro ro ro
TSS901E channel 2 status and control registers
Port Width / Address (hex) 32 30 31 32 33 34 35 16 30 31 32 33 34 35 8 30 31 32 33 34 35 Register CH2_DSM_MODR CH2_DSM_CMDR CH2_DSM_STAR CH2_DSM_TSTR CH2_ADDR CH2_RT_ADDR Function channel 2 DSM mode Register channel 2 DSM command Register channel 2 DSM status Register channel 2 DSM test Register channel 2 address Register channel 2 Route Address Register Reset Value (hex) 03 00 00 00 00 00 Access r/w r/w r/w r/w r/w r/w
9
TSS901E
Rev. C - 24-Aug-01
TSS901E
Port Width / Address (hex) 32 36 37 38 39 3A 3B 3C 3D 3E 3F 40 16 36 37 38 39 3A 3B 3C 3D 3E 3F 40 8 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F CH2_COMICFG CH2_TX_SAR CH2_CNTRL1 CH2_CNTRL2 CH2_HTID CH2_HCNTRL CH2_ESR1 CH2_ESR2 Register CH2_PR_STAR Function channel 2 Protocol Status Register reserved channel 2 control Register 1 channel 2 control Register 2 channel 2 Header Transaction ID byte channel 2 Header control byte channel 2 detailed error source register 1 channel 2 detailed error source register 2 reserved channel 2 COMI configuration register channel 2 transmit Start Address Register Reset Value (hex) 04 00 00 00 00 00 00 00 00 00 00 r/w r/w r/w r/w ro ro r/w r/w Access r/w
42
42
CH2_TX_EAR
channel 2 transmit End Address Register
00
r/w
44 46 47 48
44 46 47 48
CH2_TX_CAR CH2_TX_FIFO CH2_TX_EOPB CH2_RX_SAR
channel 2 transmit Current Address Register channel 2 transmit FIFO channel 2 transmit EOP Bit Register channel 2 receive Start Address Register
00 00 00 00
ro wo wo r/w
4A
4A
CH2_RX_EAR
channel 2 receive End Address Register
00
r/w
4C 4E 4F
4C 4E 4F
CH2_RX_CAR CH2_RX_FIFO CH2_STAR
channel 2 receive Current Address Register channel 2 receive FIFO channel 2 Status Register
00 xxxxxxxx 01
ro ro ro
TSS901E channel 3 status and control registers
Port Width / Address (hex) 32 50 51 52 16 50 51 52 8 50 51 52 Register CH3_DSM_MODR CH3_DSM_CMDR CH3_DSM_STAR Function channel 3 DSM mode Register channel 3 DSM command Register channel 3 DSM status Register Reset Value (hex) 03 00 00 Access r/w r/w r/w
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Rev. C - 24-Aug-01
Port Width / Address (hex) 32 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 16 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 8 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F CH3_COMICFG CH3_TX_SAR CH3_CNTRL1 CH3_CNTRL2 CH3_HTID CH3_HCNTRL CH3_ESR1 CH3_ESR2 Register CH3_DSM_TSTR CH3_ADDR CH3_RT_ADDR CH3__PR_STAR Function channel 3 DSM test Register channel 3 address Register channel 3 Route address Register channel 3 Protocol Status Register reserved channel 3 control Register 1 channel 3 control Register 2 channel 3 Header Transaction ID byte channel 3 Header control byte channel 3 detailed error source register 1 channel 3 detailed error source register 2 reserved channel 3 COMI configuration register channel 3 transmit Start Address Register Reset Value (hex) 00 00 00 04 00 00 00 00 00 00 00 00 00 00 r/w r/w r/w r/w ro ro r/w r/w Access r/w r/w r/w r/w
62
62
CH3_TX_EAR
channel 3 transmit End Address Register
00
r/w
64 66 67 68
64 66 67 68
CH3_TX_CAR CH3_TX_FIFO CH3_TX_EOPB CH3_RX_SAR
channel 3 transmit Current Address Register channel 3 transmit FIFO channel 3 transmit EOP Bit Register channel 3 receive Start Address Register
00 00 00 00
ro wo wo r/w
6A
6A
CH3_RX_EAR
channel 3 receive End Address Register
00
r/w
6C 6E 6F
6C 6E 6F
CH3_RX_CAR CH3_RX_FIFO CH3_STAR
channel 3 receive Current Address Register channel 3 receive FIFO channel 3 Status Register
00 xxxxxxxx 01
ro ro ro
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TSS901E
Rev. C - 24-Aug-01
TSS901E
TSS901E GPIO control registers These registers are only enabled when the TSS901E is configured for "control by link" using the 'BOOTLINK' pin.
Port Width / Address (hex) 32 16 8 70 71 72 73 74 75 76 77 Register GPIO_DIR0 GPIO_DIR1 GPIO_DIR2 GPIO_DIR3 GPIO_DATA0 GPIO_DATA1 GPIO_DATA2 GPIO_DATA3 Function GPIO direction register 0 GPIO direction register 1 GPIO direction register 2 GPIO direction register 3 GPIO data register 0 GPIO data register 1 GPIO data register 2 GPIO data register 3 Reset Value (hex) 00 00 00 00 00 00 00 00 Access r/w r/w r/w r/w r/w r/w r/w r/w
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Rev. C - 24-Aug-01
Signal Description
The Figure below shows the TSS901E (also called SMCS332) embedded in a typical module environment:
This section describes the pins of the TSS901E. Groups of pins represent busses where the highest number is the MSB. O = Output; I = Input; Z = High Impedance; (*) = active low signalO/Z = if using a configuration with two TSS901Es these signals can directly be connected together (WIROR)
max. output Signal Name HSEL* HRD* HWR* HADR(7:0) HDATA(31:0) Type I I I I IO/Z Select host interface host interface read strobe host interface write strobe TSS901E register address lines. This address lines will be used to access (address) the TSS901E registers. TSS901E data host acknowledge. TSS901E deasserts this output to add wait states to a TSS901E access. After TSS901E is ready this output will be asserted. host interrupt request line TSS901E Address. The binary value of this lines will be compared with the value of the TSS901E ID lines. TSS901E ID lines: offers possibility to use sixteen TSS901E within one HSEL* 3 50 Function current [mA] load [pF]
HACK
O/Z
3
50
HINTR* TSS901EADR(3:0 ) TSS901EID(3:0)
O/Z I
3
50
I
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TSS901E
Rev. C - 24-Aug-01
TSS901E
max. output Signal Name HOSTBIGE Type I 1: host I/F Big Endian 0: host I/F Little Endian 1: control by link 0: control by host Communication memory select lines. These pins are asserted as chip selects for the corresponding banks of the communication memory. Communication memory read strobe. This pin is asserted when the TSS901E reads data from memory. Communication memory write strobe. This pin is asserted when the TSS901E writes to data memory. Communication memory address. The TSS901E outputs an address on these pins. Communication memory data. The TSS901E inputs and outputs data from and to com. memory on these pins. Communication interface 'occupied' input signal Communication interface 'occupied' output signal Communication interface arbitration master input signal CAM I 1: master 0: slave CPUR* SES(3:0)* LDI1 LSI1 LDO1 LSO1 LEN1 LDI2 LSI2 LDO2 LSO2 LEN2 LDI3 LSI3 LDO3 LSO3 LEN3 TRST* O/Z O/Z I I O/Z O/Z O/Z I I O/Z O/Z O/Z I I O/Z O/Z O/Z I CPU Reset Signal Specific External Signals Link Data Input channel 1 Link Strobe Input channel 1 Link Data Output channel 1 Link Strobe Output channel 1 Link Enable Out (for external drivers) Link Data Input channel 2 Link Strobe Input channel 2 Link Data Output channel 2 Link Strobe Output channel 2 Link Enable Out (for external drivers) Link Data Input channel 3 Link Strobe Input channel 3 Link Data Output channel 3 Link Strobe Output channel 3 Link Enable Out (for external drivers) Test Reset. Resets the test state machine. 12 12 3 25 25 50 12 12 3 25 25 50 12 12 3 25 25 50 3 3 50 50 Function current [mA] load [pF]
BOOTLINK
I
CMCS(1:0)*
O/Z
8
25
CMRD*
O/Z
8
25
CMWR*
O/Z
8
25
CMADR(15:0)
O/Z
8
25
CMDATA(31:0) COCI COCO
IOZ I O/Z
3 3
50 50
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Rev. C - 24-Aug-01
max. output Signal Name TCK TMS TDI Type I I I Function Test Clock. Provides an asynchronous clock for JTAG boundary scan. Test Mode Select. Used to control the test state machine. Test Data Input. Provides serial data for the boundary scan logic.
tCKL Test Data Output. Serial scan output of the boundary scan tCKH path.
L
current [mA]
load [pF]
TDO
O/Z
3
50
RESET*
I
TSS901E Reset. Sets the TSS901E to a known state. This input must be asserted (low) at power-up. The minimum width of RESET low is 5 cycles of CLK10 in parallel with CLK running. External clock input to TSS901E (max. 25 Mhz). Must be derived from RAM access time. External clock input to TSS901E DS-links (application specific, nominal 10 Mhz). Used to generate to transmission speed and link disconnect timeout. Output of internal PLL. Used to connect a network of external RC devices. Power Supply Ground
CLK
I
CLK10
I
PLLOUT VCC GND
O
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TSS901E
Rev. C - 24-Aug-01
TSS901E
Electrical Specifications
The following data is provided for information only; for the guaranteed values, refer to Atmel procurement specification.
Absolute Maximum Ratings
Parameter Supply Voltage I/O Voltage Operating Temperature Range (Ambient) Junction Temperature Storage Temperature Range TA TJ Tstg Symbol VCC Value -0.5 to +7 -0.5 to VCC + 0.5 -55 to +125 TJ < TA +20 -65 to +150 Unit V V C C C
Stresses above those listed may cause permanent damage to the device.
DC Electrical Characteristics
Specified at VCC = + 5 V 10% (TSS901E will only work with 5V)
Parameter Operating Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Output Short circuit current Symbol VCC VIH VIL VOH VOL IOS 2.4 0.4 160 130 Min. 4.5 2.0 0.8 Max. 5.5 Unit V V V V V mA mA max. output current max. output current VOUT = VCC VOUT = GND Conditions
Although specified for TTL outputs, all TSS901E outputs are CMOS compatible and will drive to VCC and GND assuming no dc loads. Max. power consumption figures (at 5.5V, 125C) are:
Operation Mode not clocked TSS901E in RESET TSS901E in IDLE Maximum Power consumption [mA] 5 45 70 190
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Rev. C - 24-Aug-01
PLL Filter
The pin PLLOUT should be connected as shown below:
TSS90E
PLLOUT R1 C1 C2
R1 = 249 5%, 1/41/4W C1 = 1nF, 5%, 200V C2 = 15nF, 5%, 200V
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TSS901E
Rev. C - 24-Aug-01
TSS901E
Timing Parameters
Clock Signals
Description CLK period 1) CLK width high CLK width low
Symbol tCLK tCLKH tCLKL
Min. 40 17 17
Max.
Unit ns ns ns
Note:
1)
Max. 25 MHz
Description CLK10 period
1)
Symbol tCLK10 tCLK10H tCLK10L
Min. 100 40 40
Max. 100
Unit ns ns ns
CLK10 width high CLK10 width low
Note:
1)
Typically 10 MHz
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Rev. C - 24-Aug-01
Reset
Description RESET setup before CLK high RESET low pulse width Output disable after CLK high Output enable after CLK high CAM, HOSTBIGE, BOOTLINK setup before RESET high
Symbol tRSTS tRSTW tOUTD tOUTE tCAMS
Min. 5 2 * tCLK
Max.
Unit ns ns
42 2 * tCLK + 26 1
ns ns
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TSS901E
Rev. C - 24-Aug-01
TSS901E
Host Read
Description HSEL*, HRD* and TSS901EADR and HADR setup before CLK high HADR, TSS901EADR hold after HSEL*, HRD* high HRD* pulse width high HACK low after HRD*, HSEL* active and TSS901EADR valid 1) HACK high after CLK high HACK disable after HRD*, HSEL* inactive or TSS901EADR invalid 2) HDATA valid before HACK high HDATA hold after HRD*, HSEL* inactive or TSS901EADR invalid 2)
Symbol tHRSU tHRAH tHRDH tHRACKL tHRACKH tHRACKA tHRDV tHRDH
Min. 5 0 5
Max.
Unit ns ns ns
16 1 * tCLK + 5 3 * tCLK + 23 12 0 5 19
ns ns ns ns ns
Note:
1) Signal HACK active when HRD* low and HSEL* low and TSS901EADR = TSS901EID 2) Signal HACK disable when HRD* high or HSEL* high or TSS901EADR 1/4 TSS901EID
20
Rev. C - 24-Aug-01
Host Write
Description HSEL*, HWR* and TSS901EADR and HADR setup before CLK high HADR, TSS901EADR hold after HSEL*, HWR* high HWR* pulse width high HACK low after HWR*, HSEL* active and TSS901EADR valid
1)
Symb. tHWSU tHWAH tHWWH tHWACKL tHWACKH
2)
Min. 5 0 1 * tCLK + 5
Max.
Unit ns ns ns
16 1 * tCLK + 5 2.5 * tCLK + 24 12 5 0
ns ns ns ns ns
HACK high after HSEL* and HWR* and TSS901EADR = TSS901EID HACK disable after HWR* or HSEL* inactive or TSS901EADR invalid
tHWACKA tHWDSU tHWDH
HDATA setup before HSEL* or HWR* high or TSS901EADR TSS901EID
HDATA hold after HWR* or HSEL* inactive or TSS901EADR invalid
2)
21
TSS901E
Rev. C - 24-Aug-01
TSS901E
COMI Read
tCRCA tCRPW CMCS0 tCRCH
CLK
CMCS1 tCRCH tCRCA tCRPW CMRD
CMWR tCRCA CMADR Addr. Valid tCRCA Addr. Valid tCRPW
Addr. Valid
CMDATA tCRDS tCRDH
tCRDS tCRDH
Description CMCS0*, CMCS1* and CMRD* low and CMADR valid after CLK high CMCS0*, CMCS1* or CMRD* high after CLK high CMCS0*, CMCS1*, CMRD*, CMADR pulse width CMDATA setup before CMCS0* or CMCS1* or CMRD* high or new address on CMADR CMDATA hold after CMCS0* or CMCS1* or CMRD* high or new address on CMADR
Symbol tCRCA tCRCH tCRPW tCRDS tCRDH
Min.
Max. 18 18
Unit ns ns ns ns
tCLK - 1 4
0
ns
22
Rev. C - 24-Aug-01
COMI Write
CLK tCWCA tCWPW CMCS0 tCWCH
CMCS1 tCWCH tCWPW CMWR
tCWCA
CMRD tCWCA CMADR Addr. Valid Addr. Valid
CMDATA
Data Valid
Data Valid
tCWDE
tCWDS
tCWDH
Description CMCS0*, CMCS1* and CMWR* low and CMADR valid after CLK high CMCS0*, CMCS1* or CMWR* high after CLK high CMCS0*, CMCS1*, CMWR* pulse width CMDATA valid after CLK high CMDATA valid before CMCS0* or CMCS1* or CMWR* high CMDATA hold after CMCS0* or CMCS1* or CMWR* high
Symbol tCWCA tCWCH tCWPW tCWDE tCWDS tCWDH
Min.
Max. 18 18
Unit ns ns ns
tCLK - 1 15 25 tCLK/2 + 18
ns ns
23
TSS901E
Rev. C - 24-Aug-01
TSS901E
COMI Arbitration
Description COM Interface disable after CLK low COM Interface enable after CLK high COCI setup before CLK low COCO low after CLK low COCO high after CLK high COCO pulse width
3)
Symbol tCAID tCAIE tCOCIS tCOCOL tCOCOH tCOCOW
Min.
Max. 23 22
Unit ns ns ns
2 11 11 N - 1 tCLK
ns ns ns
Note:
3)
N = content of COMI_ACR
24
Rev. C - 24-Aug-01
CPUR, SES, Interrupt
CLK tOUTC
CPUR SESx
HINTR
Description CPUR*, SESx*, HINTR* delay after CLK high
Symbol tOUTC
Min.
Max. 22
Unit ns
Links
tLBITP LSOx LDOx tLOUT LDIx
tLDSI tLDSI
tLOUT
LSIx
Description Bit Period LDOx, LSOx output skew Data/Strobe edge separation
Symbol tLBITP tLOUTS tLDSI
Min. 4
Max.
Unit ns
0.5 1
ns ns
25
TSS901E
Rev. C - 24-Aug-01
TSS901E
Test Port (JTAG)
tTCK TCK tTCKH tTCKL tTIS tTIH
TMS TDI tTDO TDO tTRST TRST tSYSS tSYSH INPUTS tSYSO OUTPUTS
Description TCK period TCK width high TCK width low TMS, TDI setup before TCK high TMS, TDI hold after TCK high TDO delay after TCK low TRST* pulse width TSS901E Inputs setup before TCK high TSS901E Inputs hold after TCK high TSS901E Outputs delay after TCK low
Symbol tTCK tTCKH tTCKL tTIS tTIH tTDO tTRST tSYSS tSYSM tSYSO
Min. 100 40 40 8 8
Max.
Unit ns ns ns ns ns
17 2 * tTCK 8 8 27
ns ns ns ns ns
Note:
The BSDL file is printed in the Annex of this document.
26
Rev. C - 24-Aug-01
Mechanical Data
Package Dimensions
MQFPL 196
Code: FX
Date:13/10/00
27
TSS901E
Rev. C - 24-Aug-01
TSS901E
Pin Assignment
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VCC GND GND CLK RESET* CLK10 HOSTBIGE TCK TMS TDI TRST* TDO VCC GND HSEL* HRD* HWR* HACK HINTR* VCC GND HADR0 HADR1 HADR2 HADR3 HADR4 HADR5 HADR6 HADR7 VCC GND BOOTLINK TSS901EADR0 TSS901EADR1 TSS901EADR2 TSS901EADR3 TSS901EID0 TSS901EID1 TSS901EID2 TSS901EID3 VCC GND HDATA0 HDATA1 Name Pin Number 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Name HDATA18 HDATA19 HDATA20 HDATA21 HDATA22 HDATA23 VCC GND HDATA24 HDATA25 HDATA26 VCC GND HDATA27 HDATA28 HDATA29 VCC GND HDATA30 HDATA31 CPUR* SES0* SES1* SES2* SES3* CAM COCI COCO CMCS0* CMCS1* VCC GND CMRD* CMWR* CMADR0 CMADR1 CMADR2 CMADR3 CMADR4 VCC GND CMADR5 CMADR6 CMADR7 Pin Number 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Name CMDATA8 VCC GND CMDATA9 CMDATA10 CMDATA11 CMDATA12 CMDATA13 CMDATA14 VCC GND CMDATA15 CMDATA16 CMDATA17 CMDATA18 CMDATA19 CMDATA20 VCC GND CMDATA21 CMDATA22 CMDATA23 VCC GND CMDATA24 CMDATA25 CMDATA26 VCC GND CMDATA27 CMDATA28 CMDATA29 CMDATA30 CMDATA31 NC NC NC NC NC VCC GND GND LEN1 LDI1
28
Rev. C - 24-Aug-01
Pin Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
Name HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 VCC GND HDATA7 HDATA8 HDATA9 HDATA10 HDATA11 VCC GND HDATA12 HDATA13 HDATA14 HDATA15 HDATA16 HDATA17 VCC GND
Pin Number 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
Name CMADR8 CMADR9 CMADR10 CMADR11 VCC GND CMADR12 CMADR13 CMADR14 CMADR15 CMDATA0 CMDATA1 CMDATA2 VCC GND CMDATA3 CMDATA4 CMDATA5 VCC GND CMDATA6 CMDATA7
Pin Number 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 LSI1 LDO1 LSO1 LDI2 LSI2 LEN2 VCC VCC VCC LDO2 LSO2 LDI3 LSI3 LDO3 LSO3 LEN3 GND GND VCC
Name
PLLOUT
29
TSS901E
Rev. C - 24-Aug-01
TSS901E
Ordering Information
Part-number TSS901EMA-E TSS901EAM 5962-01A1701QXC TSS901EA/883(*) TSS901EASC 5962-01A1701VXC TSS901EASB TSS901EAS/883(*) TSS901EMC-E 5962-01A1701Q9A 5962-01A1701V9A Temp. Range 25C -55C +125C -55C +125C -55C +125C -55C +125C -55C +125C -55C +125C -55C +125C 25C -55C +125C -55C +125C Package MQFPL 196-pin MQFPL 196-pin MQFPL 196-pin MQFPL 196-pin MQFPL 196-pin MQFPL 196-pin MQFPL 196-pin MQFPL 196-pin Die Die Die Quality Flow Engineering sample MIL QML-Q /883S Class B SCC 9000 level C QML-V SCC 9000 level B /883S Class S Engineering sample QML-Q QML-V
(*) Contact factory
30
Rev. C - 24-Aug-01
Atmel Wireless & Microcontrollers Sales Offices
France
3, Avenue du Centre 78054 St.-Quentin-en-Yvelines Cedex France Tel: 33130 60 70 00 Fax: 33130 60 71 11
Sweden
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Hong Kong
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Germany
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United Kingdom
Easthampstead Road Bracknell, Berkshire RG12 1LX United Kingdom Tel: 441344707 300 Fax: 441344427 371
Korea
Ste.605,Singsong Bldg. Youngdeungpo-ku 150-010 Seoul Korea Tel: 8227851136 Fax: 8227851137
USA
2325 Orchard Parkway San Jose California 95131 USA-California Tel: 1408441 0311 Fax: 1408436 4200 1465 Route 31, 5th Floor Annandale New Jersey 08801 USA-New Jersey Tel: 1908848 5208 Fax: 1908848 5232
Singapore
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Taiwan
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Italy
Via Grosio, 10/8 20151 Milano Italy Tel: 390238037-1 Fax: 390238037-234
Japan
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Spain
Principe de Vergara, 112 28002 Madrid Spain Tel: 3491564 51 81 Fax: 3491562 75 14
Web site
http://www.atmel-wm.com
(c) Atmel Nantes SA, 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
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